IP Registry
Growing registry with license detection. Dependency resolution and lock files. Reproducible across machines.
rr pkg search · add · update
T₀ // entry
v4.2.0 shipped to PyPI
Agentic FPGA flow, wired end to end.
RouteRTL gives coding agents a deterministic path from requirements and IP selection through lint, simulation, synthesis, bitstream, and board validation. You stay in review and rr executes the flow.
$ pip install routertl
MIT licensed · Linux / WSL / Docker · Open source
registry · top namespaces
Registry unreachable. Browse directly →
registry.routertl.devbrowse all →
T₁ // capabilities
Run the FPGA workflow locally, in CI, or with an agent.
CI/CD & Pre-commit
Same flow locally and in CI. No drift. Configured in project.yml.
hooks.pre_commit.enabled: true
AI-Ready Workflows
Rules and schemas that AI agents can follow reliably. Pre-commit gates catch the rest.
rr testgen → scaffold → rr sim run → gate
T₂ // workflow comparison
RouteRTL replaces manual handoffs with reviewable commands.
The same FPGA work with and without a managed project flow.
topic
without RouteRTL
with RouteRTL
Dependency management
Copy-pasting source IPs between projects recursively.
Versioned modules (v4.4.1) via rr pkg add
Compilation & paths
Hardcoded absolute paths break synthesis unpredictably.
Topological sort auto-resolves identical compile orders.
Simulation tooling
Maintaining separate Makefile flows for Modelsim, Vivado, and GHDL.
One universal command: rr sim run
CI/CD & environments
Local development environment drifts slowly away from CI.
Same Docker-backed, pre-commit gated execution everywhere.
T₃ // agent-ready
agent_session.logreplaying
U
Add a UART module to the sensor hub and wire it to the main AXI bus.
A
Resolving dependencies, scaffolding tests…
$ rr pkg add open-logic/olo_base_uart
✓ extracted to vendor/open-logic/olo_base_uart
✓ updated project.yml
$ rr testgen olo_base_uart
✓ scaffolded tests/tb_uart.py
UART IP added; testbench boilerplate scaffolded. Wiring next.
Give agents reviewable commands for the FPGA workflow.
Coding agents struggle with graphical EDA tools, complex Makefiles, and undocumented TCL paths. RouteRTL provides a declarative, deterministic interface an agent can execute and an engineer can review.
Declarative CLI rules
Agents can safely execute rr sim run or rr lint without worrying about vendor-specific toolchain gotchas.
Standardised YAML schemas
From project.yml to CSR memory maps, the entire configuration layer is machine-readable by design.
Scaffolding hooks
Agents use rr testgen and rr sim scaffold to bootstrap testbenches, reducing boilerplate and letting AI focus on verification logic.
T₄ // ships for agents
MCP server
rr exposes its tooling as a Model Context Protocol server. One command wires Claude Code, Cursor, Continue, or Zed into the rr surface — agents get direct access to rr_pkg_search, rr_doctor, rr_sim_*, rr_lint_*, rr_board_*, the rules engine, and the rest via .mcp.json.
$ rr mcp install
Claude Code skills
Procedure-grade skills ship with the SDK — ip-registry-maintenance, fpga-avmm-hang-diagnose, vivado-batch-mode, zynq7-sd-boot-bringup, and more. Claude discovers them automatically when rr is installed; the right one fires for the right problem.
$ pip install routertl
T₄ // build provenance
Inspect the packages and inputs used by a build.
RouteRTL records package versions, source commits, and build targets so an engineer can inspect the inputs behind a result. Export the same bill of materials for downstream compliance tooling.
Bill of materials
List the packages, versions, source commits, and target details that make up a project.
rr bomIntegrity checks
Compare installed package files with their recorded hashes before you rely on the result.
rr pkg verifyCompliance exports
Export the bill of materials for the systems that consume CycloneDX or SPDX data.
rr bom --export cyclonedx -o sbom.cdx.jsonT₅ // requirement to evidence
Review the evidence at every step of the FPGA workflow.
An agent can repeat the flow; an engineer reviews the artifacts. Use rr hardware doctor for the connectivity preflight; board validation is captured by hardware contract runs.
T0$requirements.mdcapture intent
T1$rr init--template sensor_hub --name my_project -y
T2$rr pkg addopen-logic/olo_base_uart
T3$rr lint
T4$rr testgenolo_base_uart
T5$rr sim run
T6$rr synth runqueued target build
T7$rr bitstream runqueued target build
T8$rr hw runboard contract
what's in the box
- Register banks from YAML (VHDL · C · HTML)
- Built-in waveform viewer (RouteWave)
- VHDL / Verilog / SystemVerilog in one project
- Smart linting across the full hierarchy