A command-line workflow for FPGA development, from project setup through verification and hardware deployment.
The first-party streaming FFT core taken from its requirements catalog through hierarchy linting, cocotb simulation of the transform properties, and live requirement coverage mapping closing 12 of 12 clauses.
The contract the recording opens with: ports, parameters, and numbered requirements, written before the RTL. The lint profile it runs under, esa-vhdl-strict-provisional, is declared in project.yml.
ip: rr_fft_top
version: 0.1
hdl_file: rtl/rr_fft_top.vhd
port_contract:
slaves:
- {name: s_axis_config, protocol: axi-stream}
- {name: s_axis_data, protocol: axi-stream}
masters:
- {name: m_axis_data, protocol: axi-stream}
clocks:
- {name: aclk}
resets:
- {name: aresetn, polarity: active_low, domain: aclk}
scalars:
- {name: aclken, dir: in, width: 1}
parameters:
- { name: LOG2_N, default: 8 } # 256-pt in v1
- { name: DATA_WIDTH, default: 24 }
- { name: TWIDDLE_WIDTH, default: 24 }
- { name: NATURAL_ORDER, default: true }77 seconds: requirements catalog, smart linting, cocotb simulation, and requirement coverage mapping on the rr-fft core.
Every stage leaves reviewable evidence. A human or an agent inspects the artifacts at every stage boundary.
sim/lint.logReportsHierarchy lint of rr_fft_top: PASS.
artifacts/lint/esa-vhdl-strict-provisional.findings.jsonReportsProfile findings: 0 error, 191 warning, 0 info.
sim/cocotb/logs/regression_summary.txtSim result8 cocotb tests passed.
rr sim coverage-map .Coverage12 of 12 requirements covered by an asserted test.
project.yml and ip.yml describe the design. Autodiscovery finds the sources, the dependency resolver orders them, and lock files pin the result. The same description builds on four vendor backends with no vendor TCL.
Dependency Management (Cargo for FPGAs): IP resolves from a growing registry with license detection, ip.lock pins every dependency, and provenance and BOM reports record exactly what went into each artifact.
Each requirement stays linked to the tests, assertions, and formal properties that prove it. Coverage maps show which tests actually reached each requirement, and contract gates reject missing or vacuous evidence before it reaches CI.
Explore verification contractsThe smart linter enforces design rules for clocking, memory inference, and arithmetic before the tools run. When a vendor tool fails anyway, rr diagnose maps the log to known causes and fixes.
A SLURM-style queue arbitrates builds and simulations, leases give each user exclusive use of a shared board, and the embedded analyzer (REA) captures live signals from the running silicon.
The full loop runs through one CLI: requirement, lint, simulation, formal, synthesis, bitstream, programming, board evidence, and back to the requirement. Every step leaves an artifact an engineer can review, identical locally, in CI, and under pre-commit gates.
Explore agent workflowsip.lock pins what goes into a build; rr provenance proves what came out of it is current for the right part and target. The same records verify installed IP and export as a bill of materials.
Is the bitstream current, built from these sources, for this part and target? A non-zero exit gates the flow before a silently-wrong artifact ships.
rr provenanceEvery installed IP file is checked against the SHA-256 recorded in ip.lock — catching tampering, accidental edits, and corrupted downloads.
rr pkg verifyEvery IP with its version, commit, resolved license, tool inventory, and target device — exportable as CycloneDX or SPDX for compliance tooling.
rr bom --export cyclonedx -o sbom.cdx.jsonAn agent can repeat the flow; an engineer reviews the artifacts. Use rr hardware doctor for the connectivity preflight; board validation is captured by hardware contract runs.
what's in the box