Try RapidRTL Linting

1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.numeric_std.all;
4 
5entity counter is
6    generic (
7        G_WIDTH : natural := 8
8    );
9    port (
10        clk     : in  std_logic;
11        rst     : in  std_logic;
12        enable  : in  std_logic;
13        count   : out std_logic_vector(G_WIDTH-1 downto 0)
14    );
15end entity counter;
16 
17architecture rtl of counter is
18    signal cnt_reg : unsigned(G_WIDTH-1 downto 0);
19begin
20    process(clk)
21    begin
22        if rising_edge(clk) then
23            if rst = '1' then
24                cnt_reg <= (others => '0');
25            elsif enable = '1' then
26                cnt_reg <= cnt_reg + 1;
27            end if;
28        end if;
29    end process;
30 
31    count <= std_logic_vector(cnt_reg);
32end architecture rtl;