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One command, one result.
Short notes on the commands that make a RouteRTL project inspectable, reproducible, and ready for the next build step.
Choose the active FPGA target
Use rr target to inspect, list, and switch the project configurations under targets/.
Read the noteBring an existing vendor project under rr
Import a vendor project, inspect the generated project description, and compare results before switching workflows.
Read the noteReplay the package set from ip.lock
Install the package closure recorded by the project lock, or deliberately re-resolve it when dependencies change.
Read the noteRun one simulation through rr
Use the single simulation entry point for one test, a full test set, or a reproducible seeded run.
Read the noteInspect a synthesis plan before a long build
Use rr synth run to validate a project or a single IP, and dry-run the project-generation boundary before synthesis.
Read the noteCheck design rules before synthesis
Run the project's active FPGA design rules and inspect the rule set that will be applied.
Read the noteFreeze the project state with routertl.lock
Resolve sources, dependencies, toolchain facts, and the SDK version into a lockfile that CI can check.
Read the noteCheck the toolchain before diagnosing the project
Use rr doctor to separate missing tools, stale installs, lock drift, and project failures.
Read the noteGenerate a schematic from the RTL
Use rr schematic to produce an SVG view of a top-level RTL module before opening a vendor project.
Read the note