AXI4 & AXI-Stream
Autodetect a full AXI4 interface by prefix (AW/W/B/AR/R), or bind an AXI-Stream by TVALID/TREADY/TDATA/TLAST. Packet boundaries, beat counts, and stall regions overlay the wave.
axi4 autodetect · axi-stream bind
T₀ // logic analyzer
RouteWaveA scriptable logic analyzer for FPGA.
Decode buses, capture live from a board with triggers, and measure signal integrity in the same window that draws the waveform. Open VCD, FST, GHW, and ILA, or stream straight from hardware. Every action is an undoable, scriptable command.
$ pip install routertl && rr routewave
one workbench
RouteWave decodes the protocol running on your signals, captures them live from real hardware, measures their integrity, and links each edge back to the RTL line that produced it — the work usually split across a waveform viewer, a logic analyzer, and a scope, in one window.
T₁ // protocol decode
Decode the protocol on the wire.
Bind a handshake, an AXI interface, or a serial line and RouteWave overlays transfers, packets, and decoded frames on the wave — with an open registry for your own protocols.
Handshake overlay
Any valid/ready pair gets Transfer and Stall bands drawn behind the signals, with beat count and duplicate-beat detection. See back-pressure at a glance.
handshake bind
UART · SPI · I2C + HLA
Built-in serial decoders with high-level-analyzer stacking — raw edges decode into frames, frames stack into transactions, transactions into protocol messages.
translate · hla apply
Bring your own protocol
Describe a bus in YAML, script a decoder in Python, or drop in a compiled .so translator. The decoder registry is open — your protocol is a first-class citizen.
protocol load · hla load · plugins
T₂ // analysis
Run the analysis inside the trace.
Frequency domain, eye diagrams, memory structures, derived signals, even decoded video — the measurements you would leave the tool for are built in.
FFT & spectrum
Run an FFT on any signal and open a spectrum view for periodic content — frequency-domain analysis without leaving the trace.
fft · spectrum
Eye diagram & BER
Render eye diagrams and BER bathtub curves from a scan — SerDes and high-speed-link signal-integrity work in the same window as the waveform.
eye-ber load · bathtub
Memory decode
Read a bus as BRAM, FIFO, dual-port RAM, register file, or AXI memory. Grid layout, configurable columns, radix control, and find-by-value.
memory bram · fifo · axi · find
Virtual & derived signals
Combinational expressions — AND/OR/XOR/NAND, edge detects, compares, add/sub — become new signals. Build a virtual bus from selected bits.
virtual a XOR b · makebus
Video decode
Decode an H.264 elementary stream or raw YUV carried on the bus into a live video window — see the frames the RTL is actually producing.
video load · yuv WxH
Measure & search
Frequency, period, width, and duty-cycle at the cursor; find pulses by width, values by range, and every occurrence of a bus value.
measure · findpulse · findrange
T₃ // live capture
Capture live from hardware.
Connect to a running design and watch it live: arm triggers, drive board inputs, and sniff bus traffic as it happens.
Live capture with triggers
Stream from a source at a set rate and arm rising / falling / either-edge triggers in single, normal, or auto mode with pre/post windows. Auto-follow the head of the capture.
stream start · stream trigger
Board control
Connect a board, press / release / switch inputs from the console, and watch the response live with follow-cursor. RouteWave drives the DUT and reads its state back on the wave.
board connect · press · switch
Protocol sniffer
Multi-lane sniffer with per-lane chips, rate limiting, goto-by-index, and export — capture and triage bus traffic as it happens.
sniffer start · chips · export
T₄ // source link
From a failing edge to the RTL that caused it.
RouteWave reads the sidecars rr writes, so a waveform is connected to its source and its tests — the debugging loop closes inside the viewer.
Wave → RTL → failing test
triage loads the test map rr writes, jumps the cursor to a failing assert's time, drops a marker, and shows the RTL declaration behind the signal — waveform, expectation, and root cause in one action.
triage assert --open
Run-to-run diff
Load a second capture as a labelled source and compare; divergence between two simulation runs is highlighted directly on the wave. Catch a regression by looking at it.
compare load … as golden
Source peek
whereis and sourcepeek open the mapped RTL declaration read-only inside RouteWave — file:line for any signal, no external editor round-trip.
whereis · sourcepeek · srcmap
T₅ // rr integration
The viewer RouteRTL writes for.
Every rr sim run and rr ila capture drops sidecars next to the wave. RouteWave reads them on open — the source map, resolved parameters, memory layout, and timing anchors are already in place when the window appears.
RouteRTL writessidecarRouteWave reads
rr sim run --view<top>.fstThe sim result opens in RouteWave the moment the run finishes — no file to hunt for, no viewer to launch.
rr sim run<top>.srcmap.jsonA VHPI plugin emits a source map beside the wave, so whereis and sourcepeek resolve any signal to its RTL file:line.
cocotb autouse fixture<top>.ltmeta.jsonemit_ltmeta walks the DUT for Verilog parameters and VHDL generics; the scope tree shows resolved constants (lock icon) and timing anchors become clickable nav links.
declare memory in the testbenchreplay metadataOne memory_hint declaration for a BRAM / FIFO / dual-port / regfile / AXI-Lite interface auto-configures the RouteWave memory view.
rr ila captureJTAG → CSVOn-chip Xilinx ILA and Intel SignalTap cores bridge over JTAG into the same viewer you use for simulation.
RouteWave ships inside the SDK — rr routewave auto-installs the viewer and prefers a fresh local build — so the same window serves simulation, on-chip capture, and live streaming.
T₆ // command bus
Every action is a command.
RouteWave has no hidden GUI-only state. All 95 commands run through one console, so everything you do by hand is undoable, replayable, and scriptable — record a macro, save it, and run the exact same investigation in CI or hand it to an agent.
- —Undo / redo across the whole session
- —Macro recording + alias definitions
- —exec <script> · chain commands with ;
- —Batch mode restores a full .ltws workspace
- —Tab-completion for commands, buses, and paths
routewave · consoleCtrl+J
rw>axi4 autodetect m_axi# bind AW/W/B/AR/R by prefix
rw>handshake bind s_valid s_ready# transfer/stall bands
rw>measure between c1 c2# freq · period · width
rw>compare load golden.fst as ref# diff two runs
rw>record start probe.rwm# capture as a macro
T₇ // formats & platforms
opens
- .vcdVerilog Change Dump — eager, lazy, chunked
- .fstFast Signal Trace — lazy hierarchy (GTKWave)
- .ghwGHDL native waveform
- .csv / .ilaVivado ILA · SignalTap exports
- .ltracenative lossless JSON
- .ltwsworkspace — layout + signals + cursors
runs on
- Linuxnative · OpenGL 3.3 · AppImage
- macOSnative · Apple Silicon + Intel · DMG
- Windows 11WSL2 via WSLg — no X server
- renderinghardware-accelerated · million-transition
- scaleLOD tree · 5–10× compaction · lazy >500 MB
- installauto via rr · ~30s first run
T₈ // get started
One install, on Linux, WSL2, or macOS.
RouteWave ships with the RouteRTL SDK — a single pip install. The viewer auto-downloads on first launch.
WSL2 on Windows 11 operates natively via WSLg.
T0$pip installroutertl
T1$rr routewave
T2$rr routewavepath/to/trace.fst
T3$rr simmy_testbench --view