Daniel J. Mazure. FPGA engineer. Built RouteRTL.
I build tools for hardware engineers. RouteRTL started from the frustration of managing FPGA projects across vendor toolchains with copy-pasted scripts and manual dependency tracking.
The result is an agentic FPGA SDK that exposes dependency resolution, simulation, synthesis, bitstream generation, and board validation through one consistent flow — across Vivado, Quartus, Radiant, and Libero.
Before RouteRTL, digital design and verification for commercial FPGA projects. That background shapes every decision in the tool: it solves problems I hit myself, in production, on real hardware.
Dependency resolution. Reproducible compile orders. Same flow locally and in CI. No copy-paste between projects.
The same project description can move through Vivado, Quartus, Radiant, and Libero targets without rewriting the engineering loop.
Deterministic commands and declarative YAML give an AI agent a workflow it can repeat while a senior engineer reviews the evidence.