Daniel J. Mazure. FPGA engineer. Built RouteRTL.
I build tools for hardware engineers. RouteRTL started from the frustration of managing FPGA projects across vendor toolchains with copy-pasted scripts and manual dependency tracking.
The result is an FPGA SDK that exposes dependency resolution, simulation, synthesis, bitstream generation, and board validation through one consistent flow — across Vivado, Quartus, Radiant, and Libero.
Before RouteRTL, digital design and verification for commercial FPGA projects. That background shapes every decision in the tool: it solves problems I hit myself, in production, on real hardware.
A CLI that owns the contract of an FPGA project.
HDL autodiscovery, lockfile-pinned IP, multi-vendor synth/impl/bitstream, cocotb sim, lint, boards, Linux overlays, on-chip debug.project.ymlis the project; Vivado and Quartus become backends.
That is the right problem. Most FPGA schedules die in "whose TCL is current," "why does Alice's laptop build," and "we found the bug after P&R." RouteRTL is built to make those into process, not folklore.
Measured shape right now: ~1,800 registered capabilities, ~3,400 closed tickets, ~175 still open, live registry (~900 catalog entries), PyPI wheels, MCP for agents. This is not a weekend wrapper.
ip.lock, SHA-pinned packages, schema-gated project.yml, rr doctor. For a PM who has burned a week on 'it built on the FAE laptop,' this is the pitch. Same class of win as Cargo/npm, applied to a field that still emails .xpr files.
Vivado, Quartus Pro/Standard, Radiant, Libero from one descriptor. You do not fire the vendor specialists — you stop the project being a Vivado project. That matters if you might cost-down, second-source, or keep a Lattice SKU alive.
Contract-first (requirements.yml), adversarial sim, sim journals, 'a green bar with zero defects found is a yellow flag.' Most shops have a Makefile and a hero. RouteRTL tries to make 'did we actually attack the DUT?' a gate. That is rare, and it is the thing that protects a date once you are past bring-up.
Registry classifies permissive vs copyleft. Accidental GPL in a bitstream is a company-level event. A PM/legal pair will notice this faster than an engineer will.
JSON output, MCP, schema as source of truth, shared-bench queue/lease. If the 2026–28 plan is 'juniors + agents ship bitstreams,' this is one of the few FPGA tools that was not retrofitted for that. The Nth project on this stack should be faster than the Nth Vivado GUI project.
Board leases, bitstream identity, JTAG confinement, HPS boot, TFTP layout — encoded because they lost days. That is what you want in a toolchain vendor. FuseSoC/Edalize do not go this far into the bench.