T₀ // reference designs

Reference designs. Buildable. Version-pinned.

Each design declares its board, vendor toolchain, IP dependencies, and a verification status — sandbox-verified or community-verified. Install with rr ref install.

Browse all designs →Verification tiers

T₁ // featured

org

design

vendor

language

status

tich

vhdl-ethernet · zybo-z7-10-rmii

Zybo Z7-10 · Vivado 2024.1 · 4 deps

Xilinx

VHDL-2008

verified · sandbox

First sandbox-verified design. More landing soon. Full filterable list at /reference-designs.

T₂ // verification tiers

sandbox-verified

Built and run in the RouteRTL sandbox on a real board. Bitstream regenerates from clean checkout. Last-verified timestamp recorded.

community-verified

Verified by a known contributor on their own hardware. Public report linked. Re-verification welcomed.

claimed

Author claims the design builds. Not yet independently verified. Use at your own risk; sandbox-verification pending.