Reproducibility across machines requires explicit boundaries. This page records the vendor toolchain releases, operating systems, Python interpreters, and boards verified on the bench and in continuous integration. It also documents the operational limits of the shared project descriptor.
These specific toolchain releases are exercised in automated regression suites and on the physical test bench.
| Tool | Version | Vendor / Provider | Status | Role & Coverage |
|---|---|---|---|---|
| AMD Vivado | 2024.1 | AMD / Xilinx | Exercised | Synthesis, routing, and power report analysis verified against real Vivado 2024.1 runs on Zynq-7000 (xc7z020) and Zynq UltraScale+ targets. |
| Altera Quartus Prime Standard | 23.1std | Altera | Exercised | Synthesis, fitting, and power analysis report parsing verified against real Quartus Prime Standard 23.1std runs on Arria 10 FPGA targets. |
| Altera Quartus Prime Pro | 25.3.1 | Altera | Exercised | Agilex 5 timing analyzer report parsing and constraint validation verified against real Quartus Prime Pro 25.3.1 runs on the DE25-Standard target. |
| Microchip Libero SoC | 2025.2 | Microchip | Backend implemented, not yet bench-verified | PolarFire SoC toolchain integration; SDC constraint checking and SmartTime report parsing verified against real Libero 2025.2 runs; full place-and-route and FlashPro programming pending bench verification. |
| GHDL | v4.1.0 | Open source | Exercised | VHDL-93 and VHDL-2008 simulation backend, LLVM code generator, and compile-gate linting exercised in scheduled CI. |
| NVC | 1.19.3 | Open source | Exercised | VHDL-2008 and VHDL-2019 simulation backend, direct LLVM code generation, and mixed-language elaboration verified on bench. |
| Verilator | 5.036 | Open source | Exercised | SystemVerilog cycle-accurate compilation and linting verified against simulation and lint run logs. |
| Yosys | 0.64 | Open source (YosysHQ / oss-cad-suite) | Exercised | Open-source synthesis, netlist elaboration, and formal verification output parsing verified against oss-cad-suite yosys 0.64 runs. |
Linux and macOS are tier-1 execution environments. Windows support runs through Windows Subsystem for Linux (WSL2).
Primary host bench OS, Forgejo CI runner, and Docker simulation container base.
Distribution apt packages for modern simulators (GHDL, NVC) and primary WSL2 environment.
Official Python base images (python:3.10 and python:3.12) executing fast and heavy CI tiers.
Native macOS wheel builds and automated cibuildwheel test suite in CI.
Intel macOS wheel builds and automated cibuildwheel test suite in CI.
Supported workflow running under Ubuntu 22.04 or 24.04 in WSL2.
Full Cython-compiled wheel matrix built, stripped, and smoke-tested on every release tag.
Compiled C-extensions (.so) are verified against manylinux2014 on Linux and built natively for arm64 and x86_64 on macOS. Pure-Python wheels are rejected by release integrity gates.
Hardware runs execute on physical boards connected to automated PDU power outlets, JTAG programmers, and UART consoles.
Zynq-7000 primary verification target and peripheral bus validation.
Zynq-7000 dual-board DCC and protocol framer target.
Zynq-7000 dual-board DCC and protocol framer target.
Zynq UltraScale+ MPSoC SOM verification and Linux target.
Altera Agilex 5 E-Series FPGA target with latching power.
Microchip PolarFire SoC multi-core RISC-V FPGA target.
Sourced directly from `rr board list`:
| Board ID | Vendor | Part | Status | Pins |
|---|---|---|---|---|
| arria-10-gx-devkit | altera | 10AX115S2F45I1SG | schematic-verified | 754 |
| axe5-eagle | altera | A5ED065BB32AE4SR0 | vendor-seed | 378 |
| de10-nano | altera | 5CSEBA6U23I7 | vendor-seed | 17 |
| de25-standard | altera | A5ED013BB32AE4SCS | vendor-seed (Linux verified) | 437 |
| icebreaker | lattice | iCE40UP5K-SG48 | vendor-seed | 4 |
| kv260 | xilinx | xck26-sfvc784-2LV-c | vendor-seed | 39 |
| polarfire-soc-discovery | microchip | MPFS095T-1FCSG325E | vendor-seed | 55 |
| routeboard_rb1 | lattice | iCE40UP5K-SG48 | vendor-seed | 28 |
| zybo | xilinx | xc7z010clg400-1 | verified | 96 |
| zybo-z7-10 | xilinx | xc7z010clg400-1 | vendor-seed | 45 |
| zybo-z7-20 | xilinx | xc7z020clg400-1 | vendor-seed | 53 |
The RouteRTL project descriptor models portable RTL, verification, and hardware flows. Certain vendor-proprietary features remain outside the scope of universal automation.
RouteRTL manages portable HDL interfaces, connects register banks, and applies constraints across multiple vendor backends. RouteRTL does not synthesize proprietary encrypted IP blocks, such as closed PCIe hard macros, multi-gigabit transceivers, or hardened memory controller PHYs. Designers configure and generate those blocks using vendor IP tools or pre-packaged wrappers, then reference the resulting netlists in project.yml sources.
The portable project.yml format translates pin assignments, I/O standards, and primary clock definitions into native vendor files (.xdc for Vivado, .qsf and .sdc for Quartus, .pdc and .sdc for Libero SoC, .pcf and .lpf for Lattice and open-source flows). Proprietary physical floorplanning directives, such as Vivado Pblock physical placement or Quartus LogicLock region directives, are not translated automatically; specify those directives in vendor-specific constraint files.
High-density commercial FPGA families require valid commercial vendor license seats. Targeted compilation for Altera Agilex 5 in Quartus Prime Pro, Microchip PolarFire SoC in Libero with Synplify Pro, or large AMD UltraScale+ parts requires configured LM_LICENSE_FILE servers. Free tool editions (Vivado Standard, Quartus Prime Lite, and open-source Yosys/nextpnr) build smaller targets without external license daemons.
Open-source simulators enforce distinct language boundaries. GHDL and NVC execute VHDL standards; Verilator compiles synthesizable SystemVerilog and Verilog to C++. Mixed-language testbenches connect across interfaces through cocotb or require commercial multi-language simulators such as Questa or Vivado xsim.
Linux (Ubuntu 22.04 or 24.04) and macOS are supported execution hosts. Windows execution requires WSL2 (Ubuntu 22.04 or 24.04) or Docker containers; native Windows PowerShell and cmd.exe without WSL2 are not supported synthesis execution environments.