Altera Build Flow Analysis

This document outlines the Altera build process for the rapidrtl project, tracing the execution from the root Makefile through the TCL scripts in the tcl/altera directory.

Build Flow Diagram


flowchart TD
    subgraph root_makefile ["Makefile (Root)"]
        M_proj["make project VENDOR=altera"]
    end

    subgraph tcl_altera ["tcl/altera/"]
        env["environment.tcl (Global Config)"]
        opts["project_options.tcl (Default Options)"]
        gen_proj["gen_project.tcl (Create Project)"]
    end

    subgraph artifacts ["Build Artifacts"]
        qpf["Project File (.qpf)"]
        qsf["Settings File (.qsf)"]
    end

    %% Flow Connections
    M_proj --> gen_proj

    %% Implicit Sources
    gen_proj -.-> env
    gen_proj -.-> opts

    %% Sequential Flow
    gen_proj --> qpf
    gen_proj --> qsf

Step-by-Step Breakdown

1. Initialization: environment.tcl

Defines the project variables:

Project Structure: Root directory, project name, and working directories.
Hardware Targets: Intel/Altera part number (Default: 10M50DAF484C7G).

2. Project Creation: gen_project.tcl

Triggered by make project VENDOR=altera. The script performs the following:

Argument Parsing: Receives file lists (RTL, IP, SIM, TCL, XDC) from the Makefile.
Project Configuration:
- Initializes the Quartus project (.qpf/.qsf).
- Sources project_options.tcl (either the default or a user-provided one).
Source Management:
- Adds VHDL/Verilog files to the project.
- Handles Intel IP cores (.ip/.qip) and Platform Designer designs (.qsys).
Constraints:
- Adds SDC files for timing constraints.
- Sources TCL scripts (often used for pinout assignments in Quartus).
Custom Scripts: Sources any additional TCL scripts provided.

Key Observations