Live CLI Demo
From Zero to FPGA Project in 30 Seconds.
One command scaffolds your entire project — project.yml, Makefile, source tree and all. No configuration. No guesswork.
user@routertl:~/my_fpga_project
What just happened
project.ymlMulti-vendor project config — vendor, part, sources, simulatorMakefileBuild targets for synthesis, simulation, and lintingsrc/Source tree: units, packages, regbank stubssim/cocotb/Cocotb environment ready for Python testbenchesxdc/Constraints directory for timing & pin assignmentsverif/Verification directory for formal or coverage flows< 2s
Init time
0
Config required
3
Vendors supported
8+
Files created