T₀ // pricing
Pricing
The FPGA flow is free. The verification layer is under the Pro tier.
| feature | free | pro |
|---|---|---|
| Project + build | ||
| Declarative project.yml, source autodiscovery, dependency resolver | Included in Free | Included in Pro |
| Xilinx, Intel, Lattice, and Microchip backends | Included in Free | Included in Pro |
| Synthesis, implementation, bitstream | Included in Free | Included in Pro |
| Simulation + lint | ||
| rr sim run — nvc, GHDL, Verilator, cocotb | Included in Free | Included in Pro |
| rr linting with profiles | Included in Free | Included in Pro |
| Hardware | ||
| rr program, rr hw, board registry, virtual board | Included in Free | Included in Pro |
| rr linux — declarative rootfs, DTB, boot | Included in Free | Included in Pro |
| IP | ||
| Registry search, rr pkg add, ip.lock | Included in Free | Included in Pro |
| Verification | ||
| rr verify — verification sessions and evidence records | Not included in Free | Included in Pro |
| rr formal — PSL and SVA property checking | Not included in Free | Included in Pro |
| Coverage maps against a requirements contract | Not included in Free | Included in Pro |
| Agents | ||
| MCP server and its free-tier tools | Included in Free | Included in Pro |
| Local rr diagnose | Included in Free | Included in Pro |
| rr loop — the agentic verification loop | Not included in Free | Included in Pro |
| Licence | ||
| Support and pricing | Not included in Free | by email |