Schema-backed field inventoryrr help project.yml

project.yml

Portable configuration for one FPGA project—or many targets.

Name the design, select the hardware, and declare how it should be checked and built. Keep that complete configuration in project.yml, or use the root file to select one of several complete target configurations.

Create a project Browse configuration areas

23: top-level areas
2: required areas
4: vendor ecosystems
1: portable project model

Small by default

A working file does not need to list every source.

rr init creates the initial file. With auto_sources enabled, RouteRTL walks outward from the top module and discovers the HDL dependency graph. Add explicit configuration only when the project needs it.

rr initrr config get hardware.partrr config set hardware.part <part>rr help project.yml --all

project.ymlstarter

project:
  name: sensor_hub
  top_module: sensor_hub

hardware:
  vendor: xilinx
  part: xc7a35tcsg324-1
  language: vhdl

auto_sources: true

simulation:
  test_dir: sim/cocotb/tests
  simulator: nvc

linting:
  simulator: ghdl

Configuration boundaries

What goes where

Project intent is portable. Board variants and machine-specific coordination have their own scopes.

Portable project

project.yml

Design intent that should behave the same on a laptop, in CI, and on another supported toolchain.

Target variants

targets/<name>.yml

Complete target configurations for another board, part, language, or build profile. rr target selects the active one.

Host configuration

bench.yml + local state

Physical wiring, shared-resource ownership, queues, and telemetry stay with the machine instead of leaking into the project.

Multi-target projects

The root file selects; it does not overlay.

A self-contained project.yml holds the complete configuration. In a multi-target repository, the root file can instead contain only a target: pointer. The selected file is the complete active configuration: other settings beside the pointer are not merged into it.

# project.yml
target: targets/arty.yml

# Switch without editing the pointer
rr target set arria10

Top-level reference

Every configuration area

This inventory is checked against the live CLI. For nested fields, allowed values, and examples, run rr help project.yml <area> --all.

Project identity

Name the design and select the FPGA target.

projectrequired
Project name plus synthesis and simulation top levels.
rr help project.yml project --all
hardwarerequired
Vendor, part, language, board platform, clocks, and pin selection.
rr help project.yml hardware --all
status
Whether a target is active, parked, or intentionally set aside.
rr help project.yml status --all

Sources & composition

Describe what belongs in the design and where RouteRTL should find it.

auto_sources
Let the dependency resolver discover HDL from the selected top levels.
rr help project.yml auto_sources --all
sources
Add explicit HDL, constraints, netlists, or packaged IP when discovery is not enough.
rr help project.yml sources --all
paths
Override project-relative locations for sources and generated artifacts.
rr help project.yml paths --all
dependencies
Declare external HDL libraries fetched into the project workspace.
rr help project.yml dependencies --all
ips
Track registry packages added to the project.
rr help project.yml ips --all
packages
Describe reusable IP bundles published from the project.
rr help project.yml packages --all
system_config
Connect register-bank and system-configuration inputs.
rr help project.yml system_config --all
memory_map
Point embedded software flows at the project memory map.
rr help project.yml memory_map --all

Verification & quality

Choose discovery, simulation, linting, CDC, and evidence policy.

simulation
Simulator preference, test discovery, tags, waveforms, and run defaults.
rr help project.yml simulation --all
linting
Lint backend and project-wide lint profile.
rr help project.yml linting --all
cdc_waivers
Document reviewed clock-domain crossings with explicit justification.
rr help project.yml cdc_waivers --all
requirements
Connect verification declarations to the project.
rr help project.yml requirements --all
coverage
Configure project coverage measurement and quality gates.
rr help project.yml coverage --all

Build & delivery

Control tool execution, automation, CI, and software delivery.

build_options
Pin tool releases and select synthesis or implementation strategies.
rr help project.yml build_options --all
tcl_hooks
Preserve necessary vendor-tool hooks, especially for migrated projects.
rr help project.yml tcl_hooks --all
hooks
Run project checks and generation steps around commits and simulations.
rr help project.yml hooks --all
cicd
Set project-specific continuous-integration behavior.
rr help project.yml cicd --all
linux
Describe embedded Linux sources, boot inputs, and software payloads.
rr help project.yml linux --all
eda_memory
Set memory admission and containment policy for heavy EDA processes.
rr help project.yml eda_memory --all
features
Opt into staged project behaviors explicitly.
rr help project.yml features --all

Use the resolved model

Change configuration through rr.

rr config reads and writes dot-paths safely. rr target manages complete target variants without hand-editing the active pointer.

Open the command map

Portable configuration for one FPGA project—or many targets.

top-level areas

required areas

vendor ecosystems

portable project model

project: name: sensor_hub top_module: sensor_hub hardware: vendor: xilinx part: xc7a35tcsg324-1 language: vhdl auto_sources: true simulation: test_dir: sim/cocotb/tests simulator: nvc linting: simulator: ghdl

Sources & composition

Describe what belongs in the design and where RouteRTL should find it.

auto_sources
Let the dependency resolver discover HDL from the selected top levels.
rr help project.yml auto_sources --all
sources
Add explicit HDL, constraints, netlists, or packaged IP when discovery is not enough.
rr help project.yml sources --all
paths
Override project-relative locations for sources and generated artifacts.
rr help project.yml paths --all
dependencies
Declare external HDL libraries fetched into the project workspace.
rr help project.yml dependencies --all
ips
Track registry packages added to the project.
rr help project.yml ips --all
packages
Describe reusable IP bundles published from the project.
rr help project.yml packages --all
system_config
Connect register-bank and system-configuration inputs.
rr help project.yml system_config --all
memory_map
Point embedded software flows at the project memory map.
rr help project.yml memory_map --all