RouteRTL in practice.
Four short terminal recordings walk through the everyday flow: a first bitstream, a requirements contract with an agent in the loop, the structure of a real project, and the RouteBoard virtual board. The sessions are real; only idle time is shortened.
Zero to bitstream
78 seconds: an empty directory to a flashable iCE40 bitstream. rr init, lint, a cocotb test, yosys synthesis, nextpnr place-and-route timing-closed at 12 MHz, icepack. Open toolchain, no vendor TCL.
Requirements to evidence
Eight minutes on a real FIFO from the registry: a contract scaffolded from the FIFO’s own HDL, four declared requirements, and an agent (claude) implementing them from the contract alone. The suite passes at two of four; the coverage map fails with exit 1 until the agent closes the gap.
Project structure and builds
52 seconds: rr hierarchy renders the discovered dependency forest, rr schematic pictures the top, one IP synthesizes out of context on real Vivado, and the full project build goes through the bench queue.
RouteBoard rb-1: the virtual silicon
57 seconds: the rb-1 is a virtual board with real silicon identity (Lattice iCE40UP5K). Only an iCE40 toolchain can build for it: synthesis, timing-closed place-and-route, a real bitstream, then the same design running as a live virtual-board session.