RouteRTL in practice.
Six short recordings of the everyday flow: a first bitstream, a requirements contract with an agent in the loop, the structure of a real project, the RouteBoard virtual board, a design taken through the whole flow on a board on the bench, and a simulation opened in the RouteWave waveform viewer. The sessions are real; in the terminal recordings, only idle time is shortened.
A first bitstream on the open iCE40 toolchain
- duration 1:43
- target iCE40 UP5K · iCEBreaker
- toolchain yosys · nextpnr · icepack
An empty directory taken through rr init, lint, a cocotb test, yosys synthesis, nextpnr place-and-route closing timing at 12 MHz, and icepack. The toolchain is open throughout; there is no vendor TCL.
Tests written from a requirements contract
- duration 1:17
- target open-logic FIFO from the registry
- toolchain nvc · cocotb · coverage map
A contract scaffolded from the FIFO’s own HDL, with four declared requirements, and an agent implementing them from the contract alone. The suite passes two of four; the coverage map exits 1 until the remaining requirements are covered.
Project structure and builds
- duration 0:50
- target demo_uart_top
- toolchain Vivado · bench queue
rr hierarchy renders the discovered dependency forest, rr schematic draws the top module, one IP synthesizes out of context under Vivado, and the full project build is submitted to the bench queue.
Building for the rb-1 virtual board
- duration 1:10
- target RouteBoard rb-1 · iCE40UP5K identity
- toolchain iCE40 open toolchain
The rb-1 is a virtual board carrying an iCE40UP5K identity, so only an iCE40 toolchain can build for it: synthesis, place-and-route with timing closed, a bitstream, and then the same design running as a virtual-board session.
A live bus session on real silicon
- duration 1:26
- target Zybo Z7-20 · deepskopion data logger
- toolchain wave_stream daemon · session summary
A shared bench board taken under lease, its bitstream identity read from the design’s own register, then a mixed UART, I2C, SPI and edge workload driven on the board itself. The daemon replays recent history to any client that connects, so each record is tagged live or backfill and the summary counts only the recorded session: 518 UART bytes with no framing errors, 300 I2C transactions, 600 SPI, 2327 edges, every one of them stamped on a single microsecond clock.
A design carried through the flow on a DE25 board
- duration 4:06
- target Terasic DE25-Standard · Agilex 5
- toolchain rr lease · queue · program · ila · RouteWave
A single design carried through the flow on a Terasic DE25-Standard. The board is leased first, since the bench is shared. The project declares a board and a top module, and sources are discovered rather than listed. Lint passes; synthesis is submitted to the build queue, runs under a memory cap, and reports 978 ALMs at 366.8 MHz with timing met. The bitstream loads in five seconds. The analyzer instantiated in the design reports its version and build id from the fabric, and a 4096-sample window is read back over JTAG without SignalTap or an .stp file. RouteWave opens on that capture as it arrives; at two microseconds the state machine resolves into its four states and the sample clock into individual 50 MHz cycles. Screen recording, real time, no audio.
A simulation opened in the waveform viewer
- duration 1:41
- target open-logic FIFO · RouteWave
- toolchain nvc · cocotb · rr waves
A cocotb run against a FIFO from the registry passes four of four on nvc, and rr waves opens that same run in RouteWave with the signals named as the entity spells them. The whole run is brought into view, two cursors measure a 240 ns handshake, frequency and duty are read on hover, and the FIFO’s own level and full flag are added at the end, where the transfer stalls. Screen recording, real time, no audio.
Two ways to read one live bus
- duration 0:48
- target Zybo Z7-20 · deepskopion data logger
- toolchain wave_stream · RouteWave
RouteWave attached to a Zybo Z7-20 while the board drives its own UART, I2C, SPI and edge traffic. The message view lists every decoded transaction as it arrives — protocol, length, payload, and the time it happened — and selecting a row opens the decoded fields. The same stream then reads as waveform in the Edge Scope, where the raw line transitions sit on the identical microsecond clock as the packets above them. Screen recording, real time, no audio.