Project Initialization Guide
The rr init command is the standard entry point for creating new FPGA projects
with the RouteRTL SDK. It enforces a consistent directory structure, sets up the
build system, and configures pre-commit hooks.
Quick Start
pip install routertl rr init --template blinky --name my_project -y
Usage
rr init [OPTIONS]
Options
| Option | Description | Default |
|---|---|---|
--name | Project Name | my_fpga_project |
--template | Template to scaffold from (blinky, counter, axi) | (interactive) |
--vendor | FPGA Vendor (xilinx, lattice, altera, microchip) | xilinx |
--part | FPGA Part Number | xc7z020clg400-1 |
-y | Non-interactive mode (accept defaults) | False |
--list-templates | List available templates and exit | — |
--repair | Repair a broken project (regenerate Makefile, hooks) | — |
If no arguments are provided, the script runs in interactive mode, prompting for all necessary configuration.
Available Templates
| Template | Description |
|---|---|
blinky | Minimal: 1 SDK unit (edge_counter), 1 cocotb test |
counter | Intermediate: fifo_xpm_sync with XPM dependency |
axi | Protocol: AXI-Lite BFM verification with TbEnv |
Generated Structure
The command creates the following file organization:
project_root/ ├── project.yml # Main configuration file (single source of truth) ├── Makefile # Build system entry point ├── VERSION # Semantic version tracking ├── .gitignore # Standard git ignore rules ├── src/ │ ├── pkg/ # VHDL/SV Packages │ └── units/ # RTL Units ├── sim/ │ └── cocotb/tests/ # Cocotb testbenches ├── xdc/ # Constraints └── verif/ # Verification artifacts
Next Steps
After initialization, you can immediately run:
rr doctor— Verify your environment and tools.rr lint— Smart hierarchical linting.rr sim— Discover and run tests (interactive selection).rr sim --all— Run all tests.rr synth— Synthesize with configured vendor.