Portable project
project.ymlDesign intent that should behave the same on a laptop, in CI, and on another supported toolchain.
rr help project.ymlproject.yml
Name the design, select the hardware, and declare how it should be checked and built. Keep that complete configuration in project.yml, or use the root file to select one of several complete target configurations.
Small by default
rr init creates the initial file. With auto_sources enabled, RouteRTL walks outward from the top module and discovers the HDL dependency graph. Add explicit configuration only when the project needs it.
rr initrr config get hardware.partrr config set hardware.part <part>rr help project.yml --allproject:
name: sensor_hub
top_module: sensor_hub
hardware:
vendor: xilinx
part: xc7a35tcsg324-1
language: vhdl
auto_sources: true
simulation:
test_dir: sim/cocotb/tests
simulator: nvc
linting:
simulator: ghdlConfiguration boundaries
Project intent is portable. Board variants and machine-specific coordination have their own scopes.
project.ymlDesign intent that should behave the same on a laptop, in CI, and on another supported toolchain.
targets/<name>.ymlComplete target configurations for another board, part, language, or build profile. rr target selects the active one.
bench.yml + local statePhysical wiring, shared-resource ownership, queues, and telemetry stay with the machine instead of leaking into the project.
Top-level reference
This inventory is checked against the live CLI. For nested fields, allowed values, and examples, run rr help project.yml <area> --all.
Name the design and select the FPGA target.
projectrequiredProject name plus synthesis and simulation top levels.
rr help project.yml project --allhardwarerequiredVendor, part, language, board platform, clocks, and pin selection.
rr help project.yml hardware --allstatusWhether a target is active, parked, or intentionally set aside.
rr help project.yml status --alltargetDelegate the whole configuration to a target yml whose contents replace the root config.
rr help project.yml target --allbrandingRename the CLI for white-label distribution.
rr help project.yml branding --allDescribe what belongs in the design and where RouteRTL should find it.
auto_sourcesLet the dependency resolver discover HDL from the selected top levels.
rr help project.yml auto_sources --allsourcesAdd explicit HDL, constraints, netlists, or packaged IP when discovery is not enough.
rr help project.yml sources --allpathsOverride project-relative locations for sources and generated artifacts.
rr help project.yml paths --alldependenciesDeclare external HDL libraries fetched into the project workspace.
rr help project.yml dependencies --allipsTrack registry packages added to the project.
rr help project.yml ips --allpackagesDescribe reusable IP bundles published from the project.
rr help project.yml packages --allsystem_configConnect register-bank and system-configuration inputs.
rr help project.yml system_config --allmemory_mapPoint embedded software flows at the project memory map.
rr help project.yml memory_map --allcontractsDeclare static compatibility contracts between IP and the selected target.
rr help project.yml contracts --allChoose discovery, simulation, linting, CDC, and evidence policy.
simulationSimulator preference, test discovery, tags, waveforms, and run defaults.
rr help project.yml simulation --alllintingLint backend and project-wide lint profile.
rr help project.yml linting --allcdc_waiversDocument reviewed clock-domain crossings with explicit justification.
rr help project.yml cdc_waivers --allrequirementsConnect verification declarations to the project.
rr help project.yml requirements --allcoverageConfigure project coverage measurement and quality gates.
rr help project.yml coverage --allformalConfigure formal elaboration used to qualify proof evidence.
rr help project.yml formal --allfddSet the Firmware Design Document policy enforced by rr fdd check.
rr help project.yml fdd --allsimSet the environment simulations run under when the queue dispatches them.
rr help project.yml sim --allvboardChoose the modelled peripherals a virtual RouteBoard session instantiates.
rr help project.yml vboard --allControl tool execution, automation, CI, and software delivery.
build_optionsPin tool releases and select synthesis or implementation strategies.
rr help project.yml build_options --allbuildSet build-history retention, including recoverable bitstream snapshots.
rr help project.yml build --alltcl_hooksPreserve necessary vendor-tool hooks, especially for migrated projects.
rr help project.yml tcl_hooks --allhooksRun project checks and generation steps around commits and simulations.
rr help project.yml hooks --allcicdSet project-specific continuous-integration behavior.
rr help project.yml cicd --alllinuxDescribe embedded Linux sources, boot inputs, and software payloads.
rr help project.yml linux --alleda_memorySet memory admission and containment policy for heavy EDA processes.
rr help project.yml eda_memory --allfeaturesOpt into staged project behaviors explicitly.
rr help project.yml features --alltoolchainPick which vendor install builds this part, instead of whichever one PATH names first.
rr help project.yml toolchain --allenvironmentDeclare the environment variables the project depends on, with defaults.
rr help project.yml environment --allsynthesisSet the gates applied at the synthesis stage.
rr help project.yml synthesis --allprogrammingSet the defaults rr program uses when no CLI argument overrides them.
rr help project.yml programming --allqueueTune how the build queue admits and dispatches this project's jobs.
rr help project.yml queue --alllockTune ip.lock behavior.
rr help project.yml lock --alldockerSelect the container image used for containerized runs.
rr help project.yml docker --allmakefile_overridesOverride the directory layout of the generated Makefile.
rr help project.yml makefile_overrides --allvendor_overridesApply per-vendor knobs to the emitted vendor Tcl.
rr help project.yml vendor_overrides --allRoot-level keys kept so older project.yml files still load. Prefer the replacement in each entry.
nameSuperseded by project.name.
rr help project.yml name --allboardSuperseded by hardware.platform.
rr help project.yml board --alloutput_dirSuperseded by project.output_dir.
rr help project.yml output_dir --allstage_filesSuperseded by hooks.post_ip_gen.
rr help project.yml stage_files --all