Migrating Existing Projects to RouteRTL
Already have a Vivado project? rr migrate converts it to a RouteRTL project.yml
in minutes — no manual rewriting, no guesswork.
Overview
The migration toolset has two commands:
| Command | Purpose |
|---|---|
rr migrate run | Parse a vendor project and generate project.yml |
rr migrate verify | Compare build results between original and migrated project |
Migration is Tier 1 — it parses the .xpr XML directly. No Vivado installation
required (except for block design export).
Quick Start
# 1. Point at your Vivado project
rr migrate run /path/to/my_design.xpr .
# 2. Review the generated config
cat targets/my_design.yml
# 3. Build with RouteRTL
rr lint
rr synth run
# 4. Verify the migration
rr migrate verify --reference /path/to/my_design.xpr
rr migrate run
rr migrate run <project_file> [output_dir]
Arguments
| Argument | Required | Description |
|---|---|---|
project_file | Yes | Vendor project file (.xpr) |
output_dir | No | Target directory (default: .) |
Options
| Option | Description |
|---|---|
--targets-dir DIR | Directory for generated configs (default: targets) |
--src-dirs DIR | Extra directories to search for missing source files (repeatable) |
--name NAME | Override the project name |
--dry-run | Parse and report without writing any files |
What It Does
- Parses the
.xpr— extracts part, top module, sources, constraints, IP cores, and TCL hooks - Relocates external files — copies sources outside the project into
hw/src/,hw/xdc/, orscripts/ - Resolves IP repositories — copies IP cores into
hw/ip/ - Exports block designs — if Vivado is available, exports BD files as TCL scripts
- Generates
project.yml— complete configuration with all sources, constraints, and hooks - Scaffolds the project — creates
Makefile,.gitignore, and build environment files - Writes a migration report — summary of what was migrated, what needs attention
Generated Files
my_design/ ├── project.yml # Points to target config ├── Makefile # SDK integration ├── .gitignore # Build artifact exclusions ├── hw/ │ ├── src/ # Relocated RTL sources │ ├── xdc/ # Relocated constraints │ └── ip/ # Relocated IP cores ├── scripts/ # TCL hooks └── targets/ ├── my_design.yml # Full project configuration └── my_design.migration_report.txt # Detailed migration report
Missing File Resolution
If source files referenced in the .xpr can't be found, the migrator:
- Auto-searches in concentric rings around the
.xprfile - Searches any directories passed via
--src-dirs - Prompts interactively for additional search paths
Vivado artifact directories (.cache, .gen, .runs, etc.) are automatically skipped.
Dry Run
Preview the migration without writing anything:
rr migrate run my_design.xpr . --dry-run
This parses the project, resolves files, and prints the full migration report — but creates no files on disk.
rr migrate verify
After migrating and building, verify that the results match:
rr migrate verify --reference <original_project> [--current <migrated_root>] [--json]
Options
| Option | Required | Description |
|---|---|---|
--reference, -r | Yes | Path to original Vivado project or impl_1/ directory |
--current, -c | No | Path to migrated project root (default: .) |
--json | No | Machine-readable JSON output |
Compared Metrics
| Category | Metrics |
|---|---|
| Utilization | CLB LUTs, Registers, Block RAM, URAM, DSPs, Bonded IOB |
| Timing | WNS, TNS, WHS, THS, timing met status |
| Bitstream | File size |
Verdict
| Status | Meaning |
|---|---|
| PASS | All metrics identical or < 2% difference |
| WARN | Significant differences (>= 2%) but non-breaking |
| FAIL | Mismatches indicating a migration issue (e.g. timing regression) |
# Basic verification
rr migrate verify -r /path/to/original/vivado/project
# JSON output for CI pipelines
rr migrate verify -r /path/to/original -c . --json
Supported Formats
| Format | Vendor | Status |
|---|---|---|
.xpr | Xilinx/AMD Vivado | Supported |
.qpf / .qsf | Intel Quartus | Planned |
.rdf | Lattice Radiant | Planned |
.ldf | Lattice Diamond | Planned |
.prjx | Microchip Libero | Planned |
Block Designs
If the project contains Xilinx block designs (.bd files):
- Vivado available: auto-exports as TCL scripts and adds them as
gen_projecthooks - Vivado not available: generates a TODO placeholder in
project.yml— you can manually export from the Vivado GUI and userr hook adapt <exported_bd.tcl>
Tips
- Always run
--dry-runfirst to preview the migration - Check the migration report for flagged issues (missing files, absolute paths, unsupported features)
- After migration, run
rr doctorto verify your environment - Use
rr migrate verifyto confirm build equivalence before switching workflows