Migrating from RapidRTL to RouteRTL

This guide walks you through updating your project after the SDK rebrand.

The entire migration takes ~2 minutes. There are no behavioral changes — only the name has changed.

Step-by-Step

1. Update the Submodule Path

# Remove the old submodule
git submodule deinit -f vendor/rapidrtl
git rm -f vendor/rapidrtl
rm -rf .git/modules/vendor/rapidrtl

# Add the new submodule
git submodule add https://github.com/djmazure/routertl.git vendor/routertl
git submodule update --init --recursive

2. Update Your Makefile

 ROOT_DIR := $(shell pwd)
-include vendor/rapidrtl/tools/Common.mk
+include vendor/routertl/tools/Common.mk

3. Rename the Config Directory

mv .rapidrtl .routertl

4. Reinstall the SDK

# Remove the old venv (if any)
rm -rf .venv

# Install via pip (recommended)
pip install routertl

# Or, if keeping the submodule approach:
pip install -e vendor/routertl

# Repair project files
rr init --repair

5. Verify

# The new CLI command
routertl --help

# The shortcut still works
rr --help

# Run your tests
routertl sim --all

6. Update CI/CD (if applicable)

Search your pipeline configs for rapidrtl and replace with routertl:

# Quick find-and-replace
sed -i 's/rapidrtl/routertl/g' bitbucket-pipelines.yml
sed -i 's/RapidRTL/RouteRTL/g' bitbucket-pipelines.yml

7. Update Docker Volumes (if using Docker)

If you have existing Docker volumes from old builds:

# Remove old volumes (optional — only if you want to reclaim space)
docker volume ls | grep rapidrtl | awk '{print $2}' | xargs -r docker volume rm

# Rebuild with the new name
routertl docker install sim

What Changed

What Did NOT Change

• All Make targets work identically

• project.yml format is unchanged

• rr shortcut still works

• Python public API — the classes and functions (Tb, run_simulation, UartSource, etc.) are identical; only the top-level package name changed (rapidrtl → routertl). This is a breaking import change — update your test files:

  -from rapidrtl.sim import Tb, run_simulation
  +from routertl.sim import Tb, run_simulation
  

• RTL source code — no changes to your VHDL/Verilog files