RouteRTL Roadmap
Last updated: 2026-04-09 | Current release: v3.9.0
Overview
RouteRTL is a build system and package manager for FPGA development. This roadmap tracks shipped capabilities, active work, and planned features across all pillars.
177 capabilities shipped across 5 pillars. 25 architectural decisions recorded.
Pillars
1. IP Package Manager ("Cargo for FPGAs")
The registry at registry.routertl.dev hosts 1,961 packages across 8 namespaces. Dependency resolution, verification badges, and auto-generated search tags.
Shipped (v3.7–v3.8)
| Capability | Entry point | Since |
|---|---|---|
| Package add from registry | rr pkg add ns/name | v3.4 |
| Package search with ranked results | rr pkg search keyword | v3.4 |
| Local package add | rr pkg add --local <path> [--name entity] | v3.8 |
| Post-install lint (GHDL + Verilator) | Automatic after rr pkg add | v3.8 |
| Package test runner (3-tier) | rr pkg test ns/name [-f filter] [-p threads] | v3.8 |
| Trust badges: linted / tested | Auto-assigned during scan | v3.8 |
| Entity hierarchy (top/component/primitive) | Shown in rr pkg add --local | v3.8 |
| Auto-generated search tags (60+ FPGA terms) | From entity name + abbreviations | v3.8 |
| Registry health dashboard | /health/dashboard | v3.8 |
| IP submission pipeline | POST /v1/submit | v3.8 |
| Registry integrity CI | registry-integrity.yml (weekly) | v3.8 |
| Batch verification runner | python -m registry.batch_verify | v3.8 |
| Reseed automation | bash registry/reseed.sh | v3.8 |
Key Decisions
| ID | Decision | Rationale |
|---|---|---|
| D.15 | Registry-driven IP index | Central source of truth, not distributed |
| D.21 | Canonical key: routertl_compat | Prevent schema mismatch between generators |
| D.22 | Three-tier trust badges | Can't run every IP's tests; detect presence instead |
| D.23 | Quality gate at publish, soft check at download | Registry is the trust boundary |
| D.24 | Verified badge requires author test container | Proved with open-logic: fragile without Docker |
| D.25 | Badge naming: linted/tested/simulated/silicon-proven | No sim/HW ambiguity |
Next Up
| ID | Title | Impact |
|---|---|---|
| RTL-P2.180 | Scan more HDL repos (OSVVM, UVVM, en_cl_fix) | Grow catalog |
| RTL-P2.201 | Private package registry | Enterprise feature |
| RTL-P2.204 | ip.lock v2 — target part + toolchain + verification | Reproducibility |
| RTL-P2.205 | Archive snapshots — source tarballs in registry | Availability |
| RTL-P2.246 | Fix lint on Verilog-only projects | Bug fix |
| RTL-P3.91 | Cross-repo dependency resolution | olo_fix → en_cl_fix |
| RTL-P3.100 | ip.yml as industry standard — upstream adoption | Ecosystem |
| RTL-P3.114 | Async submission for large repos | Scalability |
| RTL-I2 | Full toolchain in registry Docker (GHDL + Verilator) | Server-side verification |
2. Build System
Multi-vendor FPGA build flow: Xilinx Vivado, Intel Quartus, Lattice Radiant. Synthesis, implementation, bitstream, and timing analysis.
Shipped
| Capability | Entry point | Since |
|---|---|---|
| Vivado synthesis + implementation + bitstream | rr synth, rr impl, rr bitstream | v1.0 |
| Quartus synthesis + timing | rr synth --vendor altera | v3.0 |
| Build environment generator | project.yml → build_env.mk + build_env.tcl | v1.0 |
| Hook system (pre/post build) | project.yml hooks: | v3.5 |
| Register bank generator | project_regbank.yml → VHDL/SV packages | v2.0 |
| Vivado project migration | rr migrate <path.xpr> | v3.7 |
Next Up
| ID | Title |
|---|---|
| RTL-P2.225 | Docker-based synthesis verification |
| RTL-P2.243 | rr migrate Tier 2: auto-export block designs |
| RTL-P2.244 | rr migrate: auto-copy files + relativise paths |
| RTL-P2.245 | rr migrate: scaffold project after config generation |
3. Simulation & Verification
cocotb-based simulation with GHDL, NVC, Verilator, Questa backends. Smart incremental linting. Test generation.
Shipped
| Capability | Entry point | Since |
|---|---|---|
| cocotb simulation (GHDL, NVC, Verilator, Questa) | rr sim <testbench> | v1.0 |
| Smart incremental linter | rr lint | v2.0 |
| Test generation from entity | rr sim testgen | v3.6 |
| Generics/parameter passthrough | rr sim --generics "WIDTH=8" | v3.7 |
| Dependency resolver (compilation order) | Automatic | v2.0 |
Next Up
| ID | Title |
|---|---|
| RTL-P3.113 | Accept 'parameters' as alias for 'generics' |
| RTL-P3.104 | rr cloud sim — hosted simulation CI |
4. Embedded Linux & SoC
App Overlay system for Zynq/MPSoC: DTG, BSP, rootfs, kernel, boot pipeline.
Shipped
| Capability | Entry point | Since |
|---|---|---|
| Device tree generation (DTG) | rr dtg | v2.0 |
| BSP generation (XSCT) | rr bsp | v2.0 |
| App Overlay framework | rr overlay | v3.0 |
| XSA auto-detection | Automatic from bitstream | v2.0 |
Next Up
| ID | Title |
|---|---|
| RTL-P2.88–92 | App Overlay payload types (cross-compile, prebuilt, download, kernel-module, rootfs) |
| RTL-P2.93–95 | Boot pipeline (FSBL, U-Boot, kernel, BOOT.bin, SD card) |
| RTL-P3.32 | App Overlay systemd service auto-enable |
| RTL-P3.34 | Embedded Linux build container |
5. Developer Experience & AI
CLI polish, IDE integration, AI-assisted workflows.
Shipped
| Capability | Entry point | Since |
|---|---|---|
| Interactive project init | rr init | v1.0 |
| Project templates (blinky, counter, axi) | rr init --template | v3.0 |
| CLI tab completion (zsh, bash, fish) | Auto-activated in .venv | v3.2 |
| Rules engine (design rules, linting policies) | rr rules check | v3.6 |
| Environment doctor | rr doctor | v3.0 |
| Shell completion | rr completion | v3.2 |
Next Up
| ID | Title |
|---|---|
| RTL-P1.29 | AI-native rr — 4-layer agent integration architecture |
| RTL-P2.217 | Community rules registry |
| RTL-P2.221 | Bundle tich-pm with routertl |
| RTL-P3.109 | MCP tool: Avrum knowledge base for Claude Code |
Release Plan
v3.8.0 (on main, pending release)
Everything from today's session: package manager overhaul, registry pipeline,
rr pkg test, badges, hierarchy, tags, search improvements, rr migrate.
v3.9.0 (next)
Focus: expanded catalog (scan more repos), private registries, ip.lock v2, Vivado migration completion.
v4.0.0 (future)
Focus: hosted FPGA CI (rr cloud), AI agent integration, boot pipeline.
Live Infrastructure
| Service | URL | Platform |
|---|---|---|
| Registry API + Dashboard | registry.routertl.dev | Fly.io |
| Website + Docs | routertl.dev | Vercel |
| fpgawisdom | fpgawisdom.com | Railway + Vercel |
| CI | GitHub Actions | GitHub |
| Source | Bitbucket (private) | Bitbucket |
This roadmap is auto-maintained alongside capabilities.json, backlog.json,
and decisions.json via the tich-pm system.